library IEEE;
use IEEE.std_logic_1164.all;

entity RxUnit is
  port (
    clk, reset : in std_logic;
    enable : in std_logic;
    rd : in std_logic;
    rxd : in std_logic;
    data : out std_logic_vector(7 downto 0);
    FErr, OErr, DRdy : out std_logic);
end RxUnit;

architecture archRxUnit of RxUnit is
	component Compteur16
		port (
			clk, reset : in std_logic;
			rxd : in std_logic;
			tmpclk, tmprxd : out std_logic);
	end component;
	component ControleReception
		port  (
		clk : in std_logic;        -- input clock, 9,6 kHz.
		enable : in std_logic;		-- input clock, 155 kHz.
		reset : in std_logic;
		rxd : in std_logic;
		rd : in std_logic;
		data : out std_logic_vector(7 downto 0);
		FErr, OErr, DRdy : out std_logic
	);
	end component;
	
	signal tmpclk, tmprxd : std_logic;

begin
	U1: Compteur16 port map (enable, reset, rxd, tmpclk, tmprxd);
	U2: ControleReception port map (tmpclk, enable, reset, tmprxd, rd, data, FErr, OErr, DRdy);
end archRxUnit;
